Processors are used for a very wide range of tasks. In designing processors, effort is made to minimize their size in order to reduce production costs and energy consumption. Particularly, it is desired to minimize the number of pins of a processor.
As processors are very complex, it is very useful during both prototyping and maintenance to view internal debugging codes of the processor. For this purpose, many processors and computer systems are designed with a small debugging area which collects debugging codes. Adding additional pins to the processor in order to output the collected debugging codes for viewing by a human user is, however, considered wasteful, particularly since debugging is performed quite rarely compared to the total utilization of the processor.
U.S. patent publication 2004/0164990 to Chan et al., titled “Method, Controller and Apparatus for Displaying BIOS Debug Message”, the disclosure of which is incorporated herein by reference, describes a display device and interface for displaying debugging codes of a processor.
A paper titled: “POST-LCD: ISA/PCI Port 80/84H Post Error Debug Card”, from Megacode technology, downloaded from http://www.megacode.com/photo.htm, on Apr. 11, 2008, the disclosure of which is entirely incorporated herein by reference, shows a display device for displaying debugging codes. This paper suggests that the debugging codes are provided to the display device over a system bus, such as an ISA or PCI bus. This, however, requires an empty slot on the bus for the display device or disconnection of one of the other devices connected to the bus. Such disconnection changes the conditions of the system being debugged, which may eliminate the cause of the problem which is to be detected and thus prevents diagnosing the problem. Furthermore, the use of the bus requires a relatively large and expensive interface which is beyond that required for the relatively simple task involved.
Other devices use a serial bus, such as SMBus, SPI or UART, to convey the debugging codes from the processor.
U.S. Pat. No. 7,313,096 to Kocalar et al., Titled: “Multiplexing a Communication Port”, suggests connecting a communication board for designing, testing and debugging a processor, in parallel to a hard disk connected to the processor, such that the processor pins used are shared therebetween. An out-of-band signal is used to indicate to the processor whether it is communicating with the hard disk or with the communication board. This solution, however, uses a special pin for selection between the hard disk and the communication board. In addition, it is intrusive in that it does not allow passive receiving of debugging signals while the processor communicates with the hard disk.
U.S. Pat. No. 6,658,545 to Dayal, titled: “Passing Internal Bus Data External to a Completed System”, the disclosure of which is entirely incorporated herein by reference, describes using a bus connecting to an external memory unit also for connecting a monitoring unit, for debugging. The bus is designed to have time periods in each cycle in which it is not used for communication with the external memory and during these periods the bus is used for transferring debugging information. This approach requires that the bus have such idle periods, and also requires complicated timing of the bus access.